A digital phase-locked loop (DPLL) provides a low power and small area alternative to analog phase-locked loops. In a DPLL, the phase offset between the local oscillator and the reference clock is quantified by a time-to-digital convertor (TDC). The measured phase is then compared to the required phase and the result is used to correct the local oscillator frequency.
A stochastic-flash-TDC is constructed of a delay-line and multiple sets of flip-flops (FFs), with each set sampling the local oscillator based on the output of a single delay element. Mismatch and process variations provide a stochastic spread of sampling delays within the sampling ensemble. This setup avails high-resolution phase quantization at the cost of high average and peak current consumptions (due to the toggling of multiple FFs in a relatively narrow window of time). The later inadvertently affects other components in a system by, e.g., causing periodic modulation of various signals at the sampling frequency—known as “spurs”.
TDC sampling may, e.g., produce spurs within a required signal bandwidth (e.g. according to a communication standard), which causes degradation of the overall system performance.
Hence, there may be a desire for an improved time-to-digital conversion technique.